1. Field of the Invention
This invention relates in general to semiconductor devices, and in particular to gallium arsenide field effect transistors and related devices.
2. Description of the Related Art
Silicon logic chips and logic families, for example transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS), have dominated the digital logic field of electronics for many years. Silicon is widely favored as a base material for semiconductor logic devices because of the ability to produce both semiconducting material (silicon) and insulating material (silicon oxide) with good electrical and mechanical properties. This combination of high quality semiconducting and insulating silicon-based materials has allowed the widespread implementation of planar growth and fabrication technologies, leading to the production of large scale integrated circuits. Therefore, silicon-based logic families include devices which are easily fabricated and are inexpensive to produce, and have gained wide acceptance. However, silicon-based devices are limited in speed and frequency bandwidth due to a relatively low carrier mobility. Materials having higher carrier mobility are preferable to silicon for many applications, and the implementation of such materials would result in the production of semiconductor devices which are faster and have a larger bandwidth than those currently fabricated using silicon.
Several alternative materials have been used to create new devices previously unavailable in silicon. One of these new materials, gallium arsenide (GaAs) is common in high frequency devices, high power microwave devices and in optoelectronic devices. However, even although gallium arsenide is widely regarded as being a superior material to silicon, because inter alia of a higher carrier mobility and higher breakdown field, GaAs has captured only a small fraction of the semiconductor device market share. The use of GaAs has been limited, in part, because it has not been possible to grow an insulating layer, such as an oxide layer, on GaAs, where the insulating layer has good electrical and mechanical properties. This has, therefore, restricted the large scale integration of GaAs using planar fabrication technologies. Consequently, reliable, high quality gallium arsenide metal-oxide-semiconductor (MOS) field effect transistors (FETs) have not been widely available. This has forced designers of digital circuits and devices to maintain the use of silicon for many applications.
A new technique has recently been developed (U.S. Pat. No. 5,262,360) for forming an oxide layer in a GaAs-based heterostructure and superlattice devices. The technique includes depositing a layer of aluminum arsenide (AlAs) where an oxide layer is desired, heating the substrate to a temperature in excess of 375.degree. C., and exposing the AlAs layer to a mixture of N.sub.2 gas and water vapor. At least partial oxidation of the AlAs layer takes place, producing one or more of the following: Al(OH).sub.3, AlO(OH) or A.sub.2 O.sub.3. The motivation for fabricating the oxide layer in the GaAs-based device was primarily to obtain an insulating layer with a low refractive index, which is advantageous for producing waveguide layers in optical devices, such as laser diodes. The electrical properties of the oxide layers thus formed have not been examined nor optimized, and their suitability for use as gate oxide layers in logic devices untested.
There is therefore a need to develop techniques of fabricating insulating layers, such as oxide layers, on GaAs-based semiconductor devices, in order that high speed, wide bandwidth semiconductor logic families become manufacturable. In addition, the insulating layers should have electrical and mechanical properties commensurate with use in planar fabrication technologies, including a high resistivity and only a nominal effects on the electrical properties of adjacent semiconductor layers. The successful implementation of an insulating layer compatible with GaAs-based semiconductor devices will lead to the production of faster, wider bandwidth circuits.